Modern integrated circuits (IC'S) contain a large number of components or elements, most of which can be classified as either storage elements (i.e., a type of memory element such as a latch or flip-flop) or gates (i.e., non-memory elements such as combinational logic gates, invertors, and the like). In the process of designing and manufacturing integrated circuits, it is desired to test integrated circuits to determine whether the components of the integrated circuit are operating in the desired fashion. To accommodate testing, many IC'S include both main circuitry (i.e., the circuitry used at least for normal, non-test operation of the chip) and test circuitry (i.e., circuitry whose only function is to achieve desired testing of the IC). Such testing typically includes both controlling and observing the storage elements inside the IC. During a typical test, the storage elements are controlled to apply test patterns and the output is observed to verify the results of the test pattern application. It would theoretically be possible to provide a set of test leads or wires running to each storage element which is to be tested, with the test leads or wires being separate from the wires used during normal functioning of the element. Because a typical integrated circuit contains a large number of storage elements, this approach is generally considered infeasible because the large number of wires running between each individual storage element and test signal input and output sites (such as peripheral pads) would consume a large portion of the available surface area of the integrated circuit and make an integrated circuit of this type unrealistically expensive.
One approach to testing integrated circuits involves providing selectable connections between storage elements to configure the storage elements as one or more shift registers. For example, as depicted in FIG. 1, an integrated circuit 10 contains a number of storage elements 12a through 12g connected to logic circuitry 14a, 14b, 14c by normal-operation leads 16a through 16p. The logic elements are, in turn, connected to input-output pads 18a through 18o. During testing operation of the chip, however, the memory elements 12a through 12g can be reconfigured, in response to a test signal, so that at least some memory elements are connected in the form of one or more shift registers. As depicted in FIG. 1, for example, the memory elements 12a through 12g are connected in a shift register for providing data from one element to the next during each shift cycle, over shift lines 20a through 20g. FIG. 2 depicts circuitry that can be used for connecting the various storage elements such as flip-flop 12 which responds to a clock signal 22, such that when data 24 is input over input line 16, the flip-flop 12 stores the data. However, when serial test data SI 26 is input over test line 28 the serial data is stored in the flip-flop 12 and output on serial test data output line 20, to be available to the downstream-connected flip-flop in response to the clock signal 22. Examples of this approach are described, for example, in Dervisoglu Bulend "Using Scan Technology for Debug and Diagnostics in a Workstation Environment" IEEE 1988 International Test Conference paper 45.2, pages 976 through 986.
As seen from FIG. 1, the shift register approach eliminates the need for an individual set of test wires running from each individual storage element to peripheral pads of the chip and, instead, provides selectively useable serial interconnect lines 20a through 20g. The shift register approach, however, has certain disadvantages. As seen in FIG. 2, it adds 2 or more gates 30a, 30b, 30c to each flip-flop, increasing IC area and cost. The additional test circuitry slows downs the circuit speed. Furthermore, long shift registers 12a through 12g require a large number of test vectors to be provided in order to fully test a complex IC, thus increasing the time needed to conduct the test and the complexity involved in designing a test to achieve the desired confidence.
U.S. Pat. No. 4,613,970 issued Sep. 23, 1986 to Mesuda et al. discloses a method for diagnosing an integrated circuit having an input memory circuit and an output memory circuit connected to each combinational circuit. An input diagnostic signal is applied to at least one input memory circuit and a diagnostic signal is read out of the output memory circuit. An address signal selects the given one of the input memory circuits. As seen in FIGS. 3 and 4 of U.S. Pat. No. 4,613,970, this approach requires six additional control lines (Ai, Bi, Yj, Qj, C2, and Gr). U.S. Pat. No. 4,739,250 of Tanizawa discloses a test circuit with a plurality of basic gates arranged in a matrix with a plurality of row selection wires and a plurality of column selection wires. The structure requires three control lines, Sci, Sli and Mi. The device of Tanizawa is configured for testing basic gate cells, rather than memory elements.